
#ifndef _DRV_ASW_IO_H_
#define _DRV_ASW_IO_H_

#ifdef __cplusplus
extern "C" {
#endif

#include "sal.h"
#include "asw/include/drv_enum.h"
#include "asw/include/drv_tbl.h"
#include "asw/include/drv_field.h"


#define Op_RW 0

#define DmaRegBlk_base            0x0C000000
#define GlobalRegBlk_base         0x0C000000
#define IntfRegBlk_base           0x0C000000
#define MibMemBlk_base            0x0C000000
#define MibRegBlk_base            0x0C000000
#define MmuRegBlk_base            0x0C000000
#define MmuMemBlk_base            0x0C000000
#define QosMemBlk_base            0x0C000000
#define QosRegBlk_base            0x0C000000
#define PeMemBlk_base             0x0C000000
#define PeRegBlk_base             0x0C000000
#define AclMemBlk_base            0x0C000000
#define ArlMemBlk_base            0x0C000000
#define ArlRegBlk_base            0x0C000000
#define FxPcs_base                  0x0
#define QsgmiiPcs_base              0x0
#define SgmiiPcs_base               0x0
#define Gpio_base                     0x0
#define Led_base                       0x0
#define Mdio_base                    0x0
#define Qspi_base                     0x0
#define Sup_base                      0x0
#define TimerSoc_base              0x0
#define WdtSoc_base                0x0
#define SupEfuse_base              0x0

#define DmaRegBlk_id              0
#define GlobalRegBlk_id           1
#define IntfRegBlk_id             2
#define MibMemBlk_id              3
#define MibRegBlk_id              4
#define MmuRegBlk_id              5
#define MmuMemBlk_id              6
#define QosMemBlk_id              7
#define QosRegBlk_id              8
#define PeMemBlk_id               9
#define PeRegBlk_id               10
#define AclMemBlk_id              11
#define ArlMemBlk_id              12
#define ArlRegBlk_id              13
#define FxPcs_id                    14
#define QsgmiiPcs_id                15
#define SgmiiPcs_id                 16
#define Gpio_id                      17
#define Led_id                       18
#define Mdio_id                    19
#define Qspi_id                     20
#define Sup_id                      21
#define TimerSoc_id             22
#define WdtSoc_id                23
#define SupEfuse_id              24

#define OP_DIRECT 0
#define OP_INDIRECT 1

#define TBL_SRAM 0
#define TBL_SRAM_MASK 1
#define TBL_HASH   2

#define DRV_PTR_VALID_CHECK(ptr) \
    if (NULL == (ptr)) \
    { \
        return -1; \
    }

#define DRV_TBL_VALID_CHECK(tbl_id) \
    if (tbl_id > MaxTblId_t) \
    { \
        return -1; \
    }

#define DRV_DBG_INFO(FMT, ...)                          \
    do                                                     \
    { \
        sal_printf(FMT, ##__VA_ARGS__); \
    } while (0)

typedef int32 (*DRV_IOCTL_CB)(uint8 lchip, uint32 tbl_id, uint32 index, uint32* data);

typedef struct drv_master_s {
    sal_mutex_t* drv_mutex[DRV_MAX_CHIP_NUM];
    DRV_IOCTL_CB  ioctl_cb[DRV_IOC_HASH_DUMP+1];  /* uint32 tbl_type:3 */
    DRV_IOCTL_CB  ioctl_mask_cb[DRV_IOC_HASH_DUMP+1];  /* uint32 tbl_type:3 */
    uint8  io_wr_dis[DRV_MAX_CHIP_NUM];
    uint8  model_en;
    uint8  valid_num; /*multi chip num*/
}drv_master_t;

extern drv_master_t *p_asw_drv_master;
extern int32 dev_fd;
#define DRV_LOCK(lchip)       sal_mutex_lock(p_asw_drv_master->drv_mutex[lchip])
#define DRV_UNLOCK(lchip)    sal_mutex_unlock(p_asw_drv_master->drv_mutex[lchip])

extern int32
drv_asw_chip_sram_tbl_read(uint8 lchip, uint32 tbl_id, uint32 index, uint32* data);

extern int32
drv_asw_chip_sram_tbl_write(uint8 lchip, uint32 tbl_id, uint32 index, uint32* data);

extern int32
drv_asw_chip_mask_tbl_read(uint8 lchip,  uint32 tbl_id, uint32 index, uint32* data);

extern int32
drv_asw_chip_mask_tbl_write(uint8 lchip,  uint32 tbl_id, uint32 index, uint32* data);

extern int32
drv_asw_chip_mask_tbl_delete(uint8 lchip, uint32 tbl_id, uint32 index, uint32* data);

extern int32
drv_asw_chip_hash_add(uint8 lchip, uint32 tbl_id, uint32 index, uint32* data);

extern int32
drv_asw_chip_hash_delete(uint8 lchip, uint32 tbl_id, uint32 index, uint32* data);

extern int32
drv_asw_chip_hash_lookup(uint8 lchip, uint32 tbl_id, uint32 index, uint32* data);

extern int32
drv_asw_chip_hash_read(uint8 lchip, uint32 tbl_id, uint32 index, uint32*data);

extern int32
drv_asw_chip_hash_write(uint8 lchip, uint32 tbl_id, uint32 index, uint32*data);

extern int32
drv_asw_chip_hash_dump(uint8 lchip, uint32 tbl_id, uint32 index, uint32* data);

#ifdef __cplusplus
}
#endif

#endif /*end of _DRV_IO_H*/

